Runset QA Engineer Vacancy at Intel

Overview:

Intel is hiring an experienced Runset QA Engineer at their Bangalore location. You will execute physical verification runsets (including DRC, LVS, illegal layer, TUC, fill, LU/IOGNAC, denall, tic, tapein merge, IPC) for Synopsys ICV, Siemens Calibre and Cadence Pegasus on chip level database, mimicking virtual tape-in

The complete details of this job are as follows:

What will you be doing:

Identify/triage clear and meaningful list of discrepancies between the 3 runsets for review and final disposition.

Candidate should have good physical verification experience with multiple tape-outs.

Folks with clarity of DRC/LVS flows and lower process node is a must.

Physical Design Verification Runset Quality Checks is the primary job function

Debug the DRC/LVS rule deck failures during regressions and document the failures to the development team

Developing the layout patterns to check every design rule in the redbook design manual and integrate them into the QA regression suite is the work nature on daily basis

Automation of central regression system and maintain and manage test bench is the crucial job function.

Qualifications for this Job:

B.Tech, 4 yrs experience or MS 2 yrs in Electrical Electronic engineering is required

Experience with ICV and Calibre Layout verification runsets along with tools like CalibreDRV background is a must

Experience working on 7nm or lower process nodes desired

Strong automationscripting skills are required Tcl PythonPerl

Desire to grow in the physical verification design career path is preferred

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