B.Tech, M.Tech, BE, ME Graduates Vacancy at Synopsys

Overview:

Synopsys is hiring an experienced ASIC Digital Design Engr, II at their Pune location.

The complete details of this job are as follows:-

Roles and Responsibilities:

The Ideal Candidate should be able to:

Verification plan development and its review

Verification environment development

Debug of simulations, including those of real signals modeled using SV for analog

RTL, GLS, Co-simulations, FW simulation & coverage closure

Deliver high quality RTL and other simulation models to customer

Participate in technical reviews and contribute actively

Participate in customer support with bring-up of IP in customer simulation environment

Participate in review of SERDES / PHY / Controller IP specification to validate compliance to protocol of interest

Follow and improve development process ensuring high quality output.

Eligibility:

Candidate should be B.E./B.Tech or M.E./M.Tech in Electronics/Telecommunication/Computers as major subjects.

Basic knowledge of HVL, or HDL like VHDL, System Verilog

Knowledge of Perl/Shell scripts

Knowledge of protocols like Ethernet, PCIe, other networking protocols

In addition the candidate should have good communication skills, be a team player with good problem solving and interpersonal skills.

To Apply for this Job, Visit official Website

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