Computer Science Graduates, Postgraduates Vacancy at Meta

Overview:

Meta is hiring an experienced ASIC Engineer, Architecture (University Grad) at their Bangalore, India locations. You will have an opportunity to work with experts in the domain of video transcode, AI/ML and other technologies to evaluate algorithms, develop functional and performance models and help architect state-of-the art hardware accelerator ASICs.

The complete details of this job are as follows:

Roles and Responsibilities

• Implement and analyze advanced algorithms and architectures for video transcode and machine learning SoCs.
• Analyze and map data center workloads to ASIC architecture develop performance and functional models at different levels of abstraction to validate the architecture.
• Work with a broad array of cross functional partners in ASIC design, verification, silicon bring-up, firmware and software development to ensure the successful production deployment of the SoCs.
• Implement architecture documentation and other collateral necessary for the use and integration of your designs.

Minimum Qualifications

• Computer Architecture coursework that has covered concepts such as microprocessor architecture, memory systems and on-chip interconnection networks.
• Familiarity with C, C++, Python or other Object Oriented Programming Languages.
• Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment.
• Currently has, or is in the process of obtaining a Bachelor’s degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.

Preferred Qualifications

• Currently has, or is in the process of obtaining, a Master’s degree in Electrical Engineering, Computer Engineering, Computer Science or similar technical fields.
• Experience and knowledge in video/image/signal processing and related standards.
• Experience and knowledge in machine learning architectures and frameworks.
• Experience in analyzing and driving power versus performance trade-offs in ASIC design.

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